Vertical field-effect transistors are used in many semiconductor devices, such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), for example. The DRAM or SRAM typically includes a memory array having a plurality of memory cells. The size of the memory device is determined in part by the size of the memory cell. A smaller memory cell is typically faster and has a smaller number of defects compared to a larger cell. A number of emerging technologies use vertical field-effect transistors to reduce the size of the memory cell.
A complementary metal-oxide-semiconductor (CMOS) technology SRAM cell typically includes both n-channel and p-channel transistors. A CMOS technology SRAM cell typically does not include both vertical n-channel and vertical p-channel transistors within the semiconductor substrate. The vertical n-channel and vertical p-channel transistors may have an undesired electron flow between each other. In order to prevent the undesired electron flow between the vertical n-channel and vertical p-channel transistors, the transistors may be placed further apart, but this causes the memory cell to be larger. A complicated field isolation process may be needed to electrically isolated the transistors from one another, but the process may be difficult to perform or need additional processing steps.
Vertical field-effect transistors are more likely to have problems because of the manner in which the source and drain regions are formed compared to planar field-effect transistors. In a planar transistor, the channel region is typically covered by the gate electrode when the source and drain regions are formed. Many vertical field-effect transistors have source and drain regions that are ion implanted during the same processing step. The channel region may be exposed during the ion implanting step. Although the channel region may receive a fraction of the total doping, the doping of the channel region may significantly alter the electrical characteristics of the transistor. Lightly-doped-drain (LDD) structures, which are part of the source and drain regions, are typically formed using sidewall spacers or winged-gate structures and graded at least in the direction of current flow to reduce hot electron degradation of the gate dielectric layer near the drain region of the field-effect transistor. The LDD structure forms a more gradual electric field within the active region near the drain region to reduce hot electron damage to the gate dielectric layer near the drain region. Vertical field-effect transistors typically do not include LDD structures. Therefore, the vertical field-effect transistor is more likely to have reliability problems caused by hot electron degradation compared to the planar transistor with a LDD structure.